The present invention relates generally to interconnects, and more particularly to a barrier for an interconnect and method of forming same.
Reduction of device dimensions and increased clock speeds strain the limits of conventional interconnect technology. For example, higher current densities required for next generation technologies present a number of problems. One problem is that increased current densities increase the likelihood of voiding and de-lamination in under bump metallurgy (BLM) structure of a device terminal. In particular, the increased current densities increase thermal diffusion and electro-migration of copper from the BLM structure to the solder joint. This failure mode is especially possible for systems employing solders with high concentrations of tin (Sn) such as the leading lead-free solders or the eutectic lead-tin (PbSn) solders.
In one approach, a nickel-only barrier was attempted. However, the presence of nickel alone was found insufficient to prevent voiding and de-lamination of titanium-tungsten (TiW), chromium-copper (CrCu) or copper (Cu) of the BLM structure, especially when the device was joined to a substrate using a nickel-gold (Ni—Au) pad. The copper is likely to diffuse through the nickel to react with tin in a high temperature storage test. Therefore, a layer of copper on top of nickel is proposed to counter balance the chemical potential for copper diffusion. Unfortunately, this requires two plating baths to deposit both nickel and copper layers.
As outlined in Ebrahimi et al., “Microstructure/mechanical properties relationship in electrodeposited Ni/Cu nanolaminates,” Materials Science and Engineering, May 2000, nickel and copper can be plated from one plating bath. In that approach, laminated nickel-copper (Ni—Cu) structures using a single sulfamate solution are provided. While the use of a single bath is advantageous, that approach, designed on generating pure nickel and pure copper layers, does not take into consideration difficulties of plating the structure in the recess of a photoresist patterned wafer.
In view of the foregoing, there is a need in the art for a barrier for an interconnect and method of forming the same that do not suffer from the problems of the related art.